In the fields of data communications and telecommunications there often exists the need to recover the timing of a critically-timed transported signal. For example, where signals are mapped or transformed for transmission into frames or packets of a particular protocol by adding overhead and/or fixed stuff information and rate justification by pointer or stuffing information, thereby altering the signal's original timing, to facilitate transport of the signals through various mediums (optical, free space, electrical conduit, etc.), upon reception these signals must then be de-mapped or inverse transformed back into the signal's original format and timing characteristics. Some transport signals have stringent timing characteristics. For example, the transport of studio quality, high definition, or standard definition digital video requires stringent timing characteristics in order to provide high quality video without lossy data compression. The critical timing specifications for video signaling are very stringent due to the nature and format of the video signal (such as the chrominance and luminance representation in component video formats), as well as the display requirements associated with interlaced active field scan and the blanking criteria inherent in video in general.
Current state-of-the-art timing synchronization systems reside in anti-jitter circuits such as the DPLL (digital phase-locked loop) architectures, which are typically FIR (finite impulse response) and IIR (infinite impulse response) filter designs. These filter designs can employ multi-rate and adaptive techniques. Various companies have designed such DPLL devices to target the telecommunications and data communications markets. However, these DPLL devices have limited programmability and are generally designed to solve specific problems and work with specific line rates and protocols (e.g. 10G SONET/SDH, OC-3/OC-12/OC-48, OTN (OTU1/2/3), GbE, 10GbE, 10GFC, DS-3 mapping, etc).
Many of the traditional approaches to solving the problem of desynchronizing, or transparent clock recovery, for a client clock with stringent jitter and wander specifications usually attempt to use a “brute force” approach or an application-specific approach. Generally, such an approach is accomplished by designing an extremely narrow, low-pass filter with an order of three or greater. Such an approach is very difficult, if not impossible, to build in hardware and is not easily programmable and adaptable under program control. Furthermore, these approaches are cumbersome, difficult to understand, very time consuming to simulate, and have questionable performance characteristics. Many of the commercially available solutions tend to solve a single problem or work with a single line rate.
Thus, what are needed are systems and methods for a timing recovery architecture that is flexible, programmable, and easily and readily adaptable to solve a broad spectrum of line rates, mapping structures, and network topologies, while at the same time solving the most stringent and demanding timing recovery requirements and removing network-induced clock jitter and wander.